Lab #5
Arithmetic Logic Unit - ALU

Objective:

• Design and build a 1-bit ALU with ADD, AND, NOT, and PASS functions.
  • Use logic hierarchy to develop your design.
• Use Cascading techniques to create a 4-bit ALU from a 1-bit ALU.
  • Learn to use the Verilog HDL to specify the design rather than using the BDE editor to capture the schematics.

NOTE: In this lab we will be coding our circuits in structural Verilog. DO NOT use schematic entry from now on in labs.

Preparation:

Document the design of the ALU. 

1. Design the Full Adder circuit. (truth table, k-maps, equations)

The Full Adder will have three inputs and two outputs.

Inputs:

The three inputs consist of one bit for number A, one bit for number B, and a Carry-In.

Outputs:

The outputs are the Sum and Carry-Out. The Sum is the addition of A, B, and Cin. The Carry-Out will be used as the input into another ALU when we implement a multi-bit ALU using cascading.

See the Verilog module creation tutorial for details on how to create a Verilog module in Project Navigator.

Specify your design as a Verilog Module using built-in logic primitives (and, not, pass) as building blocks. See the Verilog Tutorial and the Verilog presentation slides for details.

Inputs Outputs Carry In A B Sum Carry Out 0 0 0     0 0 1     0 1 0     0 1 1     1 0 0     1 0 1     1 1 0     1 1 1
Full Adder Truth Table	Full Adder Component Block	Full Adder Verilog

2. Design the 1-bit ALU in Verilog code using the Full Adder module, a multiplexer and logic gates.
   • The ALU contains logical operators – AND, NOT, and PASS - as well as an Arithmetic operator - ADD.
     • Make sure the carry out is active ONLY during the ADD function.
   • Control bits will specify which operation should be performed.
     • Because this ALU will have four different operations, it is necessary to have two control bits to select which operation is to be performed. For this lab, you'll need to design a 4-to-1 multiplexer module using Verilog built-in logic primitives. See the Verilog Tutorial and the Verilog presentation slides for details.

The diagram below shows what a block diagram of the 1-bit ALU might look like. You will not be entering your design into Project Navigator as a schematic but rather you will be specifying your design as a Verilog module.

ALU Truth Table
Control		Function Select	Result	Cout
C1	C0
0	0	PASS	A	0
0	1	ADD	A+B	Carry from A+B
1	0	AND	A • B	0
1	1	NOT	A’	0

Procedure:

See the Verilog module creation tutorial for details on how to create a Verilog module in Project Navigator.

1. Generate the Verilog code for the full adder.
1. Create the TCL file and in simulation exhaustively test the Full Adder.
   
   
2. Utilizing the Full-adder Verilog module you just created, make a new module for the 1-bit ALU. 
   1. Don't forget to build and test your 4-to-1 multiplexer.
      • Generate a new TCL file and in simulation exhaustively test the 4-to-1 mux
   2. Generate a new TCL file and in simulation exhaustively test the 1-bit ALU.
      
      
3. Using your 1 bit-ALU module, create a new module for the 4-bit ALU
   1. Cascade four 1-bit ALU's together. See the Verilog Tutorial and the Verilog presentation slides for details.
      
      
4. Simulate several functions with the four bit ALU.  (Verify that each function works with a few sets of binary numbers.) See the Advanced TCL file and UCF file tutorial for examples.
   Hint: The Cin to the 4-bit ALU should always be '0'.
5. Create a .ucf  file to test the circuit on the Digilab circuit board. Use the following I/O assignments.
   

   Signal	Assignment	Notes
   Binary Number A	SW 7-4	-- Make sure your bits are in the correct order! (SW 7 is the most significant bit)
   Binary Number B	SW 3-0	-- SW 3 is the most significant bit
   Control Bit 1	BTN 3
   Control Bit 0	BTN 2
   Result	LD 3-0	-- LD 3 is the most significant bit
   Carry Out	LD 7

6. Request a PASSOFF from the TA, After you have tested your circuit.