Lab #7
Register File

 

Objective:


Preparation:

All of the design has been done as a paper exercise in Homework #7.

 


Procedure:

One bit register

We will build the 1-bit register from two modules: a 2 to1 mux and a D-type flip flop with a falling edge triggered clock and a synchronous reset. The code for the flip flop is given below:

 

// D-type flip flop with falling edge triggered clock and synchronous reset
module fd_c(q, clk, d, clr);
input clk, clr, d;
output reg q;
always @(negedge clk)
if (clr) q <= 0;
else q <= d;
endmodule

 

WARNING:  When you create your flip flop using the HDE wizard, it will create your  Q  output as a wire. The generated code will look like this:

output q;
wire q;

In this case, q is not a wire so you will have to change its declaration in the generated Verilog code. The corrected declaration looks like this:
output reg q;

A schematic for the register might look like the following:

If you used a 2 to1 multiplexer as a building block in Lab 5, you can reuse it in this lab. (See the Module Reuse tutorial for details). If you didn't use one in Lab 5, then you'll have to create one for this lab. (See the Verilog Tutorial and the Verilog presentation slides for details).

A symbol for the 1-bit register would look like the following:

  1. Build your 1-bit register from the Verilog modules and simulate it to verify that it is correct.   Don't forget to clear the register at the beginning of the simulation. When changing input signals during a simulation, you should ensure that the signals are NOT changing on a clock edge. The output waveform for this testing the 1-bit register should resemble the following:
  2. Document the Verilog modules, the TCL file and the simulation in files which you will export.

Four bit register

  1. Using the module for the one bit register and referring to the homework, construct a register word consisting of 4 bits. A symbol for the 4-bit register would look like the following:

  2. Reg
  3. Simulate it to verify that it is correct.
  4. Document the Verilog modules, the TCL file and the simulation in files which you will put in your lab report.

Four word registers

  1. Design a 4-bit word by 4 word set of registers (4 registers of 4 bits each).
  2. Simulate the register file to verify that it is correct.
  3. Document the Verilog file, the TCL file and the simulation.

Sixteen to four MUX

  1. Build the 16 to 4 multiplexer that you designed in the homework.

  2. The symbol for a 16 to 4 multiplexer would look like the following:
  3. Simulate it to verify that it is correct.
  4. Document the Verilog file, the TCL file and the simulation..

Complete four word by four bit register file

  1. Using the module for the 16 to 4 multiplexer and your 4 word register and referring to the homework, construct  a complete register file.
  2. Document the Verilog file.
  3. Test Bench (a testing circuit)

    1. Using your new 4 bit by 4 word register file, construct a test bench to test it on the Xilinx board.
    4 data input bits:Switches 7-4-- Make sure your bits are in the correct order! (SW 7 is the most significant bit)
    4 data input bit indicators:LEDs 7-4-- LED 7 is the most significant bit
    2 write address input bits:Switches 3-2-- SW 3 is the MSB
    2 read address input bits:Switches 1-0-- SW 1 is the MSB
    4 register file output bits:LEDs 3-0-- LED 3 is the MSB
    1 write control signal:Button 3 
    1 clear control signal:Button 0 
    clock signalSystem clock 

    NOTE 1:
    The 4 data bits which drive the indicator LEDs 7-4 MUST be outputs in your test bench module. This data comes to the circuit as input from switches. The same signals cannot be both inputs and outputs. You therefore will need to buffer the input signals with the built-in  BUF logic function. The outputs from the buffers can then be brought out to drive the LEDs in the .ucf file.

    example:

    buf(Din_led3,Din[3]);
    code in your test bench module

    NET Din_led3 LOC = P11; #LD7
    code in your .ucf file

    Do this for all four of the Din input signals

    NOTE 2:
    You should use the GCLK signal as your clock input. The GCLK signal can be mapped to your clock input within the .ucf  file as follows:

    NET Clk LOC = T9; # GCLK

    Implement the Design - download to the board for testing

    1. Following the same steps as you did in the previous labs, Implement the design.
    2. Test the results of  your design.
    3. Pass-off after your test bench is working correctly.