| Name |
Lecture Title |
PDF |
| INTRO |
Introduction and Overview |
PDF |
| INTRO2 |
Introduction to Digital Systems |
PDF |
| BA1 |
Boolean Algebra 1 |
PDF |
| GATES1 |
Gates 1 |
PDF |
| BA2 |
Boolean Algebra 2 |
PDF |
| GATES2 |
Gates 2 |
PDF |
| KM |
Karnaugh Maps |
PDF |
| MUX |
Multiplexers, Decoders, and ROMs |
PDF |
| NUMBERS |
Number Systems and Binary Encodings |
PDF |
| ARTH |
Arithmetic Circuits |
PDF |
| VERILOG1 |
Structural Verilog |
PDF |
| TANLYS |
Timing Analysis and Hazards |
PDF |
| VERILOG2 |
Dataflow Verilog |
PDF |
| LATCH |
Latches |
PDF |
| MSFF |
Flip Flops |
PDF |
| REGISTERS |
Registers and Register Files |
PDF |
| VERILOG3 |
Behavioral Verilog |
PDF |
| COUNTERS |
Counters |
PDF |
| COUNTERSI |
Counters with Inputs |
PDF |
| STATEGRAPHS |
State Graphs |
PDF |
| FSM |
Finite State Machines |
PDF |
| ONEHOT |
One-hot Encoding |
PDF |
| CASCNT |
Cascaded Counters |
PDF |
| LC3-1 |
LC-3 Overview |
PDF |
| LC3-2 |
The LC-3 Datapath |
PDF |
| ASYNCH |
Asynchronous Input Handling |
PDF |
| UART |
Universal Asynchronous Receiver/Transmitter |
PDF |
| LC3-3 |
LC-3 Control |
PDF |
| LC3-DC |
Designing the LC-3 Control |
PDF |
| uSEQ |
Microsequencers |
PDF |
| FPGA |
Field Programmable Gate Arrays |
PDF |
| MULT |
Binary Multiplication |
PDF |
| DEBOUNCE |
Switch Debounce Design Example |
PDF |
| SODA |
Soda Machine Design Example |
PDF |
| SILICON |
Silicon Chip Design |
PDF |